1. Field of the Invention
The present invention generally relates to a technique of increasing the withstand voltage of a semiconductor device, and more particularly, to a technique of increasing the withstand voltage and providing higher withstand strength against destruction.
2. Discussion of the Relevant Art
In the technical field of power semiconductor devices, RESURF structure devices have been studied as promising means for achieving increased withstand voltage.
The reference numeral 101 in FIG. 38 denotes a conventional MOSFET type semiconductor device, in which an N type resistance layer 112 having a large resistance value is epitaxially grown on an N-type substrate 111 having a small resistance value.
At the inner surface of the resistance layer 112, a plurality of P-type guard regions 146b whose two-dimensional shape is a square ring are concentrically formed.
In the region surrounded by the innermost guard region 146b, a plurality of long and narrow P-type base diffusion regions 117 are formed, and a long and narrow P-type Ohmic diffusion region 120 having a higher surface concentration than that of the base diffusion region 117 is provided in the widthwise center of the inside surface of each of the base diffusion regions 117.
A long and narrow N-type source diffusion region 121 is provided parallel to the Ohmic diffusion region 120 on either side of the Ohmic diffusion region 120 on the inside surface of the base diffusion region 117.
At the inside surface of the base diffusion region 117, the part between the outer periphery of the source diffusion region 121 and the outer periphery of the base diffusion region 117 forms a channel region 122, on which a gate insulating film 134 and a gate electrode film 136 are provided in the above-mentioned order.
An interlayer insulating film 137 is provided on the gate electrode film 136, and a source electrode film 138 in contact with the source diffusion region 121 and the Ohmic diffusion region 120 is provided on the interlayer insulating film 137. The source electrode film 138 is isolated from the gate electrode film 136 by the interlayer insulating film 137.
Therefore, the source electrode film 138 is insulated from the gate electrode film 136, and the source electrode film 138 is electrically connected to the source diffusion region 121 and also electrically connected to the base diffusion region 117 through the Ohmic diffusion region 120. A protective film 139 is formed on the surface of the source electrode film 138.
The drain electrode film 130 is formed on the back surface of the substrate 111. As the source electrode film 138 is grounded, a positive voltage is applied to the drain electrode film 130 and a voltage equal to or larger than the threshold voltage is applied to the gate electrode film 136 so that the channel region 122 inverted to N-type, and the source diffusion region 121 and the resistance layer 112 are connected to the inversion layer. This state is a conduction state, in which current flows from the drain electrode film 130 to the source electrode film 138.
Once the gate electrode film 136 attains a potential equal to that of the source electrode film 138, the inversion layer disappears. As a result, current no longer flows so that a cutoff state is attained.
A P-type base buried region 146a is provided at the bottom of the base diffusion region 117 in contact with the base diffusion region 117. In the cutoff state, a PN junction between the P-type region including the base diffusion region 117 and the base buried region 146a and the N-type region including the resistance layer 112 is reversely biased so that depletion layers greatly expand from both PN junctions in the base diffusion region 117 and the base buried layer 146a toward both the P-type region and the N-type region.
The base buried region 146a is a long and narrow region that extends in the extending direction of the long and narrow base diffusion region 117 and is provided in the widthwise center of each of the base diffusion regions 117.
The base diffusion regions 117 are provided parallel to one another and the base buried regions 146a are positioned parallel to one another. The depletion layers extending laterally from the base buried regions 146a are connected in the central position between the adjacent base buried regions 146a in the central position so that the resistance layer 112 between the base buried regions 146a is filled with the depletion layer.
When the depletion layer extending laterally outwardly from the base buried region 146a and the base diffusion region 117 reach the guard region 146b, the depletion layer start to expand from the guard region 146b. 
If the quantity of the N-type impurity and the quantity of P-type impurity contained in the RESURF region on the inside the widthwise center of the innermost guard region 146b and positioned between the bottom of the base buried region 146a and the bottom of the base diffusion region 117 are set to be equal. When the exact amount of voltage that causes the N-type region in the RESURF region to be filled with depletion layer is applied, the P-type region in the RESURF region is filled with the depletion layer as well.
In this state, the bottom surface of the depletion layer in the RESURF region is flat, and therefore if voltage larger than the voltage is applied and the depletion layer expands toward the substrate 111 beyond the bottom of the base buried region 146a, it appears as if the depletion layer has expanded from a planer junction, which advantageously raises the withstand voltage. The quantities of impurities and the diffusion structure that allow such depletion layers to form are called “RESURF condition.”
These relevant arts are disclosed in Japanese Patent Laid-Open Publication No. 2003-101022 and Japanese Patent Laid-Open Publication No. 2003-86800.